K60P100M100SF2RM Datasheet, PDF (1685/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 53 Integrated interchip sound (I2S)
53.3.1 I²S Transmit Data Registers 0 (I2Sx_TX0)
The TX0 registers store the data to be transmitted by the I2S.
Addresses: I2S0_TX0 is 4002_F000h base + 0h offset = 4002_F000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TX0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TX0 field descriptions
Field
31–0
TX0
Description
I2S transmit data
I²S transmit data. These bits store the data to be transmitted by the I²S. These are implemented as the
first word of their respective Tx FIFOs. Data written to these registers transfers to the transmit shift
register (TXSR), when shifting of the previous data is complete. If both FIFOs are in use, data alternately
transfers from TX0 and TX1 to TXSR. TX1 can only be used in two-channel mode. Multiple writes to the
TX registers do not result in the previous data being over-written by the subsequent data. Instead they are
ignored. Protection from over-writing is present irrespective of whether the transmitter is enabled or not.
Example: If Tx FIFO0 is in use and you write Data1 - 16 to TX0, Data16 does not overwrite Data1. Data1 -
15 are stored in the FIFO while Data16 is discarded. Example: If Tx FIFO0 is not in use and you write
Data1, Data2 to TX0, then Data2 does not overwrite Data1 and is discarded.
NOTE: Enable I²S (CR[I2SEN]=1) before writing to the I²S transmit data registers.
53.3.2 I²S Transmit Data Registers 1 (I2Sx_TX1)
The TX1 registers store the data to be transmitted by the I2S.
Addresses: I2S0_TX1 is 4002_F000h base + 4h offset = 4002_F004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TX1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TX1 field descriptions
Field
31–0
TX1
Description
I2S transmit data
I²S transmit data. These bits store the data to be transmitted by the I²S. These are implemented as the
first word of their respective Tx FIFOs. Data written to these registers transfers to the transmit shift
register (TXSR), when shifting of the previous data is complete. If both FIFOs are in use, data alternately
transfers from TX0 and TX1 to TXSR. TX1 can only be used in two-channel mode. Multiple writes to the
TX registers do not result in the previous data being over-written by the subsequent data. Instead they are
ignored. Protection from over-writing is present irrespective of whether the transmitter is enabled or not.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1685