K60P100M100SF2RM Datasheet, PDF (51/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
52.2.2 SDHC block diagram...................................................................................................................................1568
52.2.3 Features........................................................................................................................................................1569
52.2.4 Modes and operations..................................................................................................................................1570
52.3 SDHC signal descriptions.............................................................................................................................................1571
52.4 Memory map and register definition.............................................................................................................................1572
52.4.1 DMA System Address Register (SDHC_DSADDR)..................................................................................1573
52.4.2 Block Attributes Register (SDHC_BLKATTR)..........................................................................................1574
52.4.3 Command Argument Register (SDHC_CMDARG)....................................................................................1575
52.4.4 Transfer Type Register (SDHC_XFERTYP)..............................................................................................1576
52.4.5 Command Response 0 (SDHC_CMDRSP0)...............................................................................................1580
52.4.6 Command Response 1 (SDHC_CMDRSP1)...............................................................................................1581
52.4.7 Command Response 2 (SDHC_CMDRSP2)...............................................................................................1581
52.4.8 Command Response 3 (SDHC_CMDRSP3)...............................................................................................1581
52.4.9 Buffer Data Port Register (SDHC_DATPORT)..........................................................................................1583
52.4.10 Present State Register (SDHC_PRSSTAT).................................................................................................1583
52.4.11 Protocol Control Register (SDHC_PROCTL).............................................................................................1588
52.4.12 System Control Register (SDHC_SYSCTL)...............................................................................................1592
52.4.13 Interrupt Status Register (SDHC_IRQSTAT).............................................................................................1595
52.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN)............................................................................1601
52.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN)...............................................................................1604
52.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)...........................................................................1606
52.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)....................................................................................1609
52.4.18 Watermark Level Register (SDHC_WML).................................................................................................1611
52.4.19 Force Event Register (SDHC_FEVT)..........................................................................................................1611
52.4.20 ADMA Error Status Register (SDHC_ADMAES)......................................................................................1614
52.4.21 ADMA System Address Register (SDHC_ADSADDR).............................................................................1616
52.4.22 Vendor Specific Register (SDHC_VENDOR)............................................................................................1616
52.4.23 MMC Boot Register (SDHC_MMCBOOT)................................................................................................1618
52.4.24 Host Controller Version (SDHC_HOSTVER)............................................................................................1619
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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