K60P100M100SF2RM Datasheet, PDF (1151/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
ENET_TCR field descriptions
Field
31–10
Reserved
9
CRCFWD
8
ADDINS
7–5
ADDSEL
Description
This read-only field is reserved and always has the value zero.
Forward frame from application with CRC
0 TxBD[TC] controls whether the frame has a CRC from the application
1 The transmitter does not append any CRC to transmitted frames as it is expecting a frame with CRC
from the application.
Set MAC address on transmit
0 The source MAC address is not modified by the MAC.
1 The MAC overwrites the source MAC address with the programmed MAC address according to
ADDSEL.
Source MAC address select on transmit
If ADDINS is set, indicates the MAC address that overwrites the source MAC address.
4
RFC_PAUSE
3
TFC_PAUSE
000 Node MAC address programmed on PADDR1/2 registers.
100 Reserved
101 Reserved
110 Reserved
Receive frame control pause
This status bit is set when a full duplex flow control pause frame is received and the transmitter pauses for
the duration defined in this pause frame. This bit automatically clears when the pause duration is
complete.
Transmit frame control pause
Pauses frame transmission. When this bit is set, EIR[GRA] is set. With transmission of data frames
stopped, the MAC transmits a MAC control PAUSE frame. Next, the MAC clears TFC_PAUSE and
resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a
PAUSE frame, the MAC may continue transmitting a MAC control PAUSE frame.
2
FDEN
1
Reserved
0
GTS
0 No PAUSE frame transmitted.
1 The MAC stops transmission of data frames after the current transmission is complete.
Full duplex enable
If this bit set, frames transmit independent of carrier sense and collision inputs. Only modify this bit when
ECR[ETHER_EN] is cleared.
This read-only field is reserved and always has the value zero.
Graceful transmit stop
When this bit is set, MAC stops transmission after any frame currently transmitted is complete and
EIR[GRA] is set. If frame transmission is not currently underway, the GRA interrupt is asserted
immediately. After transmission finishes, clear GTS to restart. The next frame in the transmit FIFO is then
transmitted. If an early collision occurs during transmission when GTS is set, transmission stops after the
collision. The frame is transmitted again after GTS is cleared. There may be old frames in the transmit
FIFO that transmit when GTS is reasserted. To avoid this, clear ECR[ETHER_EN] following the GRA
interrupt.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1151