K60P100M100SF2RM Datasheet, PDF (420/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
DMAMUX memory map
Absolute
address
(hex)
Register name
4002_1000 Channel Configuration Register (DMAMUX_CHCFG0)
4002_1001 Channel Configuration Register (DMAMUX_CHCFG1)
4002_1002 Channel Configuration Register (DMAMUX_CHCFG2)
4002_1003 Channel Configuration Register (DMAMUX_CHCFG3)
4002_1004 Channel Configuration Register (DMAMUX_CHCFG4)
4002_1005 Channel Configuration Register (DMAMUX_CHCFG5)
4002_1006 Channel Configuration Register (DMAMUX_CHCFG6)
4002_1007 Channel Configuration Register (DMAMUX_CHCFG7)
4002_1008 Channel Configuration Register (DMAMUX_CHCFG8)
4002_1009 Channel Configuration Register (DMAMUX_CHCFG9)
4002_100A Channel Configuration Register (DMAMUX_CHCFG10)
4002_100B Channel Configuration Register (DMAMUX_CHCFG11)
4002_100C Channel Configuration Register (DMAMUX_CHCFG12)
4002_100D Channel Configuration Register (DMAMUX_CHCFG13)
4002_100E Channel Configuration Register (DMAMUX_CHCFG14)
4002_100F Channel Configuration Register (DMAMUX_CHCFG15)
Width
(in bits)
Access
Reset value
Section/
page
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
00h
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20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same Source value
will result in unpredictable behavior.
NOTE
Before changing the trigger or source settings a DMA channel
must be disabled via the CHCFGn[ENBL] bit.
Addresses: 4002_1000h base + 0h offset + (1d × n), where n = 0d to 15d
Bit
7
6
5
4
3
2
1
0
Read
Write
ENBL
TRIG
SOURCE
Reset
0
0
0
0
0
0
0
0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
420
Freescale Semiconductor, Inc.