K60P100M100SF2RM Datasheet, PDF (1423/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

49.4.3.1 Baud Rate Generator
Chapter 49 SPI (DSPI)
The Baud Rate is the frequency of the Serial Communication Clock (SCK). The system
clock is divided by a prescaler (PBR) and scaler (BR) to produce SCK with the
possibility of halving the scaler division. The DBR, PBR and BR fields in the CTAR
registers select the frequency of SCK by the formula in the BR field description. The
following table shows an example of how to compute the baud rate.
Table 49-106. Baud Rate Computation Example
f_sys
100 MHz
20 MHz
PBR
0b00
0b00
Prescaler
2
2
BR
0b0000
0b0000
Scaler
2
2
DBR
0
1
Baud Rate
25 Mb/s
10 Mb/s
NOTE
The clock frequencies mentioned in the preceding table are
given as an example. Refer to the clocking chapter for the
frequency used to drive this module in the device.
49.4.3.2 PCS to SCK Delay (t_CSC)
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first
SCK edge. See Figure 49-94 for an illustration of the PCS to SCK delay. The PCSSCK
and CSSCK fields in the CTARx registers select the PCS to SCK delay by the formula in
the CSSCK field description. The following table shows an example of how to compute
the PCS to SCK delay.
Table 49-107. PCS to SCK Delay Computation Example
f_sys
100 MHz
PCSSCK
0b01
Prescaler
3
CSSCK
0b0100
Scaler
32
PCS to SCK Delay
0.96 μs
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1423