K60P100M100SF2RM Datasheet, PDF (245/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 10 Signal Multiplexing and Signal Descriptions
Chip signal name
RMII0_MDIO
Module signal name
RMII_MDIO
RMII0_CRS_DV
RMII_CRS_DV
RMII0_RXD[1:0]
RMII0_RXER
RMII0_TXD[1:0]
RMII0_TXEN
RMII_RXD[1:0]
RMII_RXER
RMII_TXD[1:0]
RMII_TXEN
Internal OSCERCLK clock¹ RMII_REF_CLK
Description
I/O
Transfers control information I/O
between the external PHY
and the media-access
controller. Data is
synchronous to MDC. This
signal is an input after reset.
Asserting this input indicates I
the PHY has valid nibbles
present on the MII. RXDV
must remain asserted from
the first recovered nibble of
the frame through to the last
nibble. Asserting RXDV must
start no later than the SFD
and exclude any EOF.
In RMII mode, this pin also
generates the CRS signal.
Contains the Ethernet input I
data transferred from the
PHY to the media-access
controller when RXDV is
asserted.
When asserted with RXDV, I
indicates the PHY detects an
error in the current frame.
The serial output Ethernet
O
data and only valid during the
assertion of TXEN.
Indicates when valid nibbles O
are present on the MII. This
signal is asserted with the
first nibble of a preamble and
is negated before the first
TXCLK following the final
nibble of the frame.
In RMII mode, this signal is I
the reference clock for
receive, transmit, and the
control interface.
Table 10-19. USB FS OTG Signal Descriptions
Chip signal name
Module signal Description
I/O
name
USB0_DM
usb_dm
USB D- analog data signal on the USB bus.
I/O
USB0_DP
usb_dp
USB D+ analog data signal on the USB bus.
I/O
USB_CLKIN
—
Alternate USB clock input
I
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
245