K60P100M100SF2RM Datasheet, PDF (1147/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
6–1
MII_SPEED
0
Reserved
Chapter 44 10/100-Mbps Ethernet MAC (ENET)
ENET_MSCR field descriptions (continued)
Description
Enables/disables prepending a preamble to the MII management frame. The MII standard allows the
preamble to be dropped if the attached PHY devices do not require it.
0 Preamble enabled.
1 Preamble (32 ones) is not prepended to the MII management frame.
MII speed
Controls the frequency of the MII management interface clock (MDC) relative to the internal module clock.
A value of 0 in this field turns off MDC and leaves it in low voltage state. Any non-zero value results in the
MDC frequency of:
1/((MII_SPEED + 1) x 2) of the internal module clock frequency
This read-only field is reserved and always has the value zero.
44.3.8 MIB Control Register (ENET_MIBC)
MIBC is a read/write register controlling and observing the state of the MIB block.
Access this register to disable the MIB block operation or clear the MIB counters. The
MIB_DIS bit resets to 1.
Address: ENET_MIBC is 400C_0000h base + 64h offset = 400C_0064h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
MIB_
IDLE
0
W
Reset 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENET_MIBC field descriptions
Field
31
MIB_DIS
30
MIB_IDLE
Disable MIB logic
Description
If this control bit is set, the MIB logic halts and does not update any MIB counters.
MIB idle
If this status bit is set, the MIB block is not currently updating any MIB counters.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1147