K60P100M100SF2RM Datasheet, PDF (1584/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
Address: SDHC_PRSSTAT is 400B_1000h base + 24h offset = 400B_1024h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DLSL
CLSL
0
CINS
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
RTA
DLA
W
Reset 0
Field
31–24
DLSL
23
CLSL
22–17
Reserved
16
CINS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDHC_PRSSTAT field descriptions
DAT Line Signal Level
Description
This status is used to check the DAT line level to recover from errors, and for debugging.This is especially
useful in detecting the busy signal level from DAT[0]. The reset value is effected by the external pullup/
pulldown resistors. By default, the read value of this bit field after reset is 8’b11110111, when DAT[3] is
pulled down and the other lines are pulled up.
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
Data 0 line signal level
Data 1 line signal level
Data 2 line signal level
Data 3 line signal level
Data 4 line signal level
Data 5 line signal level
Data 6 line signal level
Data 7 line signal level
CMD Line Signal Level
This status is used to check the CMD line level to recover from errors, and for debugging. The reset value
is effected by the external pullup/pulldown resistor, by default, the read value of this bit after reset is 1b,
when the command line is pulled up.
This read-only field is reserved and always has the value zero.
Card Inserted
This bit indicates whether a card has been inserted. The SDHC debounces this signal so that the host
driver will not need to wait for it to stabilize. Changing from a 0 to 1 generates a card insertion interrupt in
the interrupt status register. Changing from a 1 to 0 generates a card removal interrupt in the interrupt
status register. A write to the force event register does not effect this bit.
Table continues on the next page...
1584
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.