K60P100M100SF2RM Datasheet, PDF (318/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
13.1.3.4 Multi-Clock Generator (MCG) Loss-of-Clock (LOC) Reset
The MCG module supports an external reference clock. If the clock monitor is enabled
(MCG_C6[CME] is set) and the external reference falls below a certain frequency
(specified in the MCG_C2[RANGE] field), the MCU resets. If a loss of clock causes a
reset, the SRSL[LOC] bit is set.
For more details on the clock generator, see Multi-Clock Generator (MCG).
13.1.3.5 Low-Voltage Detect (LVD) Reset
If LVDRE is set, the LVD generates a reset upon detection of a low voltage condition.
After an LVD reset has occurred, the LVD system holds the MCU in reset until the
supply voltage rises above the LVD threshold (specified by the LVDV bits). The
SRSL[LVD] bit is set following an LVD reset or POR.
13.1.3.6 Low Leakage Mode Recovery
The LLWU provides the means for up to 16 external pins, the RESET pin, and seven
internal peripherals to wake the device from LLS and VLLS power modes. When in
VLLS mode, all enabled inputs to the LLWU will generate a system reset flow when
detected. When in LLS mode, only a detected RESET pin results in a recovery via a reset
flow.
For LLS mode exits via RESET pin and any VLLS mode via a wakeup or reset event, the
MC_SRS[WAKEUP] is set indicating a low-leakage mode was active prior to the last
system reset flow. Using the RESET pin to trigger an exit from LLS or VLLS results in
the MC_SRS[PIN] being set as well.
After the system reset, the LLWU continues to retain the flags indicating the source of
wakeup until the user clears them or the next LLS or VLLS entry occurs.
NOTE
External pin flags are cleared by software via the LLWU
registers and internal peripheral module flags are required to be
cleared in associated peripheral's registers. Refer to the
individual peripheral chapters for more information.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
318
Freescale Semiconductor, Inc.