K60P100M100SF2RM Datasheet, PDF (1432/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
t_DT
Figure 49-98. Continuous SCK Timing Diagram (CONT=0)
If the CONT bit in the TX FIFO entry is set, PCS remains asserted between the transfers.
Under certain conditions, SCK can continue with PCS asserted, but with no data being
shifted out of SOUT (SOUT pulled high). This can cause the slave to receive incorrect
data. Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
• Continuous SCK with CONT bit set and entering STOPPED state (refer to Start and
Stop of DSPI Transfers).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable
mode.
The following figure shows timing diagram for Continuous SCK format with Continuous
Selection enabled.
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
transfer 1
transfer 2
Figure 49-99. Continuous SCK Timing Diagram (CONT=1)
1432
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.