K60P100M100SF2RM Datasheet, PDF (1425/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 49 SPI (DSPI)
49.4.3.5 Peripheral Chip Select Strobe Enable (PCSS )
The PCSS signal provides a delay to allow the PCS signals to settle after a transition
occurs thereby avoiding glitches. When the DSPI is in master mode and the PCSSE bit is
set in the MCR, PCSS provides a signal for an external demultiplexer to decode the
PCS[0] - PCS[4] signals into as many as 128 glitch-free PCS signals. The following
figure shows the timing of the PCSS signal relative to PCS signals.
PCSx
PCSS
t_PCSSCK
t_PASC
Figure 49-93. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS signals and the assertion of PCSS is selected
by the PCSSCK field in the CTAR based on the following formula:
At the end of the transfer the delay between PCSS negation and PCS negation is selected
by the PASC field in the CTAR based on the following formula:
The following table shows an example of how to compute the t_pcssck delay.
Table 49-110. Peripheral Chip Select Strobe Assert Computation Example
f_sys
100 MHz
PCSSCK
0b11
Prescaler
7
Delay before Transfer
70.0 ns
The following table shows an example of how to compute the t_pasc delay.
Table 49-111. Peripheral Chip Select Strobe Negate Computation Example
f_sys
100 MHz
PASC
0b11
Prescaler
7
Delay after Transfer
70.0 ns
The PCSS signal is not supported when Continuous Serial Communication SCK mode
are enabled.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1425