K60P100M100SF2RM Datasheet, PDF (1590/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_PROCTL field descriptions (continued)
Field
Description
This bit is valid only in 4-bit mode, of the SDIO card, and selects a sample point in the interrupt cycle.
Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. Setting to 0 disables
interrupt detection during a multiple block transfer. If the SDIO card can't signal an interrupt during a
multiple block transfer, this bit should be set to 0 to avoid an inadvertent interrupt. When the host driver
detects an SDIO card insertion, it shall set this bit according to the CCCR of the card.
18
RWCTL
0b Disabled
1b Enabled
Read Wait Control
The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use
of the read wait protocol to stop read data using the DAT[2] line. Otherwise the SDHC has to stop the SD
Clock to hold read data, which restricts commands generation. When the host driver detects an SDIO
card insertion, it shall set this bit according to the CCCR of the card. If the card does not support read
wait, this bit shall never be set to 1, otherwise DAT line conflicts may occur. If this bit is set to 0, stop at
block gap during read operation is also supported, but the SDHC will stop the SD Clock to pause reading
operation.
17
CREQ
0b Disable read wait control, and stop SD clock at block gap when SABGREQ bit is set.
1b Enable read wait control, and assert read wait without stopping SD clock at block gap when
SABGREQ bit is set.
Continue Request
This bit is used to restart a transaction which was stopped using the PROCTL[SABGREQ]. When a
suspend operation is not accepted by the card, it is also by setting this bit to restart the paused transfer.
To cancel stop at the block gap, set PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer.
The SDHC automatically clears this bit, therefore it is not necessary for the host driver to set this bit to 0.
If both PROCTL[SABGREQ] and this bit are 1, the continue request is ignored.
16
SABGREQ
0b No effect
1b Restart
Stop At Block Gap Request
This bit is used to stop executing a transaction at the next block gap for both DMA and non-DMA
transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a transfer completion, the host driver shall
leave this bit set to 1. Clearing both the PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the
transaction to restart. Read Wait is used to stop the read transaction at the block gap. The SDHC will
honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires that the SDIO card
support read wait. Therefore, the host driver shall not set this bit during read transfers unless the SDIO
card supports read wait and has set the PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus
clock to pause the read operation during block gap. In the case of write transfers in which the host driver
writes data to the data port register, the host driver shall set this bit after all block data is written. If this bit
is set to 1, the host driver shall not write data to the data port register after a block is sent. Once this bit is
set, the host driver shall not clear this bit before the IRQSTATEN[TCSEN] is set, otherwise the SDHC's
behavior is undefined.
This bit effects PRSSTAT[RTA], PRSSTAT[WTA], PRSSTAT[CDIHB].
15–10
Reserved
0b Transfer
1b Stop
This read-only field is reserved and always has the value zero.
Table continues on the next page...
1590
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.