K60P100M100SF2RM Datasheet, PDF (1798/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/Application information
single bit (the bypass register) while conducting an EXTEST type of instruction through
the boundary scan register. CLAMP also asserts the internal system reset for the MCU to
force a predictable internal state.
56.4.4.8 BYPASS instruction
BYPASS selects the bypass register, creating a single-bit shift register path between TDI
and TDO. BYPASS enhances test efficiency by reducing the overall shift path when no
test operation of the MCU is required. This allows more rapid movement of test data to
and from other components on a board that are required to perform test functions. While
the BYPASS instruction is active the system logic operates normally.
56.4.5 Boundary scan
The boundary scan technique allows signals at component boundaries to be controlled
and observed through the shift-register stage associated with each pad. Each stage is part
of a larger boundary scan register cell, and cells for each pad are interconnected serially
to form a shift-register chain around the border of the design. The boundary scan register
consists of this shift-register chain, and is connected between TDI and TDO when the
EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register
chain contains a serial input and serial output, as well as clock and control signals.
56.5 Initialization/Application information
The test logic is a static logic design, and TCK can be stopped in either a high or low
state without loss of data. However, the system clock is not synchronized to TCK
internally. Any mixed operation using both the test logic and the system functional logic
requires external synchronization.
To initialize the JTAGC block and enable access to registers, the following sequence is
required:
1. Place the JTAGC in reset through TAP controller state machine transitions controlled
by TMS
2. Load the appropriate instruction for the test or action to be performed
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.