K60P100M100SF2RM Datasheet, PDF (1509/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
3
RXFE
2–0
RXFIFOSIZE
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_PFIFO field descriptions (continued)
Description
101 Transmit FIFO/Buffer Depth = 64 Datawords.
110 Transmit FIFO/Buffer Depth = 128 Datawords.
111 Reserved.
Receive FIFO Enable
When this bit is set the built in FIFO structure for the receive buffer is enabled. The size of the FIFO
structure is indicated by the RXFIFOSIZE field. If this bit is not set then the receive buffer operates as a
FIFO of depth one dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
cleared prior to changing this bit. Additionally TXFLUSH and RXFLUSH commands should be issued
immediately after changing this bit.
0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
Receive FIFO. Buffer Depth
The maximum number of receive datawords that can be stored in the receive buffer before an overrun
occurs. This field is read only.
000 Receive FIFO/Buffer Depth = 1 Dataword.
001 Receive FIFO/Buffer Depth = 4 Datawords.
010 Receive FIFO/Buffer Depth = 8 Datawords.
011 Receive FIFO/Buffer Depth = 16 Datawords.
100 Receive FIFO/Buffer Depth = 32 Datawords.
101 Receive FIFO/Buffer Depth = 64 Datawords.
110 Receive FIFO/Buffer Depth = 128 Datawords.
111 Reserved.
51.3.17 UART FIFO Control Register (UARTx_CFIFO)
This register provides the ability to program various control bits for FIFO operation. This
register may be read or written at any time. Note that writing the TXFLUSH and
RXFLUSH bits may result in data loss and requires careful action to prevent unintended /
unpredictable behavior, hence it is recommended that TE and RE be cleared prior to
flushing the corresponding FIFO.
Addresses: UART0_CFIFO is 4006_A000h base + 11h offset = 4006_A011h
UART1_CFIFO is 4006_B000h base + 11h offset = 4006_B011h
UART2_CFIFO is 4006_C000h base + 11h offset = 4006_C011h
UART3_CFIFO is 4006_D000h base + 11h offset = 4006_D011h
UART4_CFIFO is 400E_A000h base + 11h offset = 400E_A011h
Bit
7
6
5
Read
0
0
Write TXFLUSH RXFLUSH
Reset
0
0
0
4
3
0
0
0
2
1
0
TXOFE
RXUFE
0
0
0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1509