K60P100M100SF2RM Datasheet, PDF (296/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SIM_CLKDIV1 field descriptions (continued)
Field
27–24
OUTDIV2
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Divide-by-5.
Divide-by-6.
Divide-by-7.
Divide-by-8.
Divide-by-9.
Divide-by-10.
Divide-by-11.
Divide-by-12.
Divide-by-13.
Divide-by-14.
Divide-by-15.
Divide-by-16.
Clock 2 output divider value
Description
This field sets the divide value for the peripheral clock. At the end of reset, it is loaded with either 0000 or
0111 depending on FTFL_FOPT[LPBOOT].
23–20
OUTDIV3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Divide-by-1.
Divide-by-2.
Divide-by-3.
Divide-by-4.
Divide-by-5.
Divide-by-6.
Divide-by-7.
Divide-by-8.
Divide-by-9.
Divide-by-10.
Divide-by-11.
Divide-by-12.
Divide-by-13.
Divide-by-14.
Divide-by-15.
Divide-by-16.
Clock 3 output divider value
This field sets the divide value for the FlexBus clock driven to the external pin (FB_CLK). At the end of
reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT].
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Divide-by-1.
Divide-by-2.
Divide-by-3.
Divide-by-4.
Divide-by-5.
Divide-by-6.
Divide-by-7.
Divide-by-8.
Divide-by-9.
Divide-by-10.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
296
Freescale Semiconductor, Inc.