K60P100M100SF2RM Datasheet, PDF (1443/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 50
Inter-Integrated Circuit (I2C)
50.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The inter-integrated circuit (I²C, I2C, or IIC) module provides a method of
communication between a number of devices. The interface is designed to operate up to
100 kbit/s with maximum bus loading and timing. The device is capable of operating at
higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are
limited by a maximum bus capacitance of 400 pF. The I2C module also complies with
the System Management Bus (SMBus) Specification, version 2.
50.1.1 Features
The I2C module has the following features:
• Compatible with The I²C-Bus Specification
• Multimaster operation
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1443