K60P100M100SF2RM Datasheet, PDF (1400/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
SPIx_MCR field descriptions (continued)
Field
27
FRZ
Freeze
Description
Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug
mode.
26
MTFE
0 Do not halt serial transfers in debug mode.
1 Halt serial transfers in debug mode.
Modified Timing Format Enable
Enables a modified transfer format to be used.
25
PCSSE
0 Modified SPI transfer format disabled.
1 Modified SPI transfer format enabled.
Peripheral Chip Select Strobe Enable
Enables the PCS[5]/ PCSS to operate as a PCS Strobe output signal.
24
ROOE
0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal.
1 PCS[5]/PCSS is used as an active-low PCS Strobe signal.
Receive FIFO Overflow Overwrite Enable
In the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or overwrite
existing data. If the RX FIFO is full and new data is received, the data from the transfer, generating the
overflow, is ignored or shifted into the shift register.
23–22
Reserved
21–16
PCSIS[5:0]
0 Incoming data is ignored.
1 Incoming data is shifted into the shift register.
This read-only field is reserved and always has the value zero.
Peripheral Chip Select x Inactive State
Determines the inactive state of PCSx.
15
DOZE
0 The inactive state of PCSx is low.
1 The inactive state of PCSx is high.
Doze Enable
Provides support for an externally controlled Doze mode power-saving mechanism.
14
MDIS
0 Doze mode has no effect on DSPI.
1 Doze mode disables DSPI.
Module Disable
Allows the clock to be stopped to the non-memory mapped logic in the DSPI effectively putting the DSPI
in a software controlled power-saving state. The reset value of the MDIS bit is parameterized, with a
default reset value of "0".
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.
Table continues on the next page...
1400
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.