K60P100M100SF2RM Datasheet, PDF (1582/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
Table 52-13. Response bit definition for each response type
Response type
R1,R1b (normal response)
R1b (Auto CMD12 response)
R2 (CID, CSD register)
Meaning of response
Card status
Card status for auto CMD12
CID/CSD register [127:8]
R3 (OCR register)
R4 (OCR register)
R5, R5b
R6 (Publish RCA)
OCR register for memory
OCR register for I/O etc.
SDIO response
New published RCA[31:16]
and card status[15:0]
Response field
R[39:8]
R[39:8]
R[127:8]
R[39:8]
R[39:8]
R[39:8]
R[39:9]
Response register
CMDRSP0
CMDRSP3
{CMDRSP3[23:0],
CMDRSP2, CMDRSP1,
CMDRSP0}
CMDRSP0
CMDRSP0
CMDRSP0
CMDRSP0
This table shows that most responses with a length of 48 (R[47:0]) have 32-bit of the
response data (R[39:8]) stored in the CMDRSP0 register. Responses of type R1b (auto
CMD12 responses) have response data bits (R[39:8]) stored in the CMDRSP3 register.
Responses with length 136 (R[135:0]) have 120-bit of the response data (R[127:8]) stored
in the CMDRSP0, 1, 2, and 3 registers.
To be able to read the response status efficiently, the SDHC only stores part of the
response data in the command response registers. This enables the host driver to
efficiently read 32-bit of response data in one read cycle on a 32-bit bus system. Parts of
the response, the index field and the CRC, are checked by the SDHC (as specified by the
XFERTYP[CICEN] and the XFERTYP[CCCEN] bits) and generate an error interrupt if
any error is detected. The bit range for the CRC check depends on the response length. If
the response length is 48, the SDHC will check R[47:1], and if the response length is 136
the SDHC will check R[119:1].
Since the SDHC may have a multiple block data transfer executing concurrently with a
CMD_wo_DAT command, the SDHC stores the auto CMD12 response in the CMDRSP3
register. The CMD_wo_DAT response is stored in CMDRSP0. This allows the SDHC to
avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.
When the SDHC modifies part of the command response registers, as shown in the table
above, it preserves the unmodified bits.
Address: SDHC_CMDRSP3 is 400B_1000h base + 1Ch offset = 400B_101Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMDRSP3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1582
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.