K60P100M100SF2RM Datasheet, PDF (1623/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
The SDHC will not start data transmission until the number of words set in the WML
register can be held in the buffer. If the buffer is empty and the host system does not
write data in time, the SDHC will stop the SD_CLK to avoid the data buffer under-run
situation.
52.5.1.2 Read operation sequence
There are three ways to read data from the buffer when the user transfers data to the card:
1. By using the external DMA through the SDHC DMA request signal
2. By processor core polling through the IRQSTAT[BRR] bit (interrupt or polling)
3. By using the internal DMA
When internal DMA is not used (i.e. XFERTYP[DMAEN] bit is not set when the
command is sent), the SDHC asserts a DMA request when the amount of data exceeds
the value set in the WML register, that is available and ready for system fetching data. At
the same time, the SDHC would set the IRQSTAT[BRR] bit. The buffer read ready
interrupt will be generated if it is enabled by software.
When internal DMA is used, the SDHC will not inform the system before all the required
number of bytes are transferred (if no error was encountered). When an error occurs
during the data transfer, the SDHC will abort the data transfer and abandon the current
block. The host driver should read the content of the DMA system address register to get
the starting address of the abandoned data block. If the current data transfer is in multi
block mode, the SDHC will not automatically send CMD12, even though the
XFERTYP[AC12EN] bit is set. The host driver shall send CMD12 in this scenario and
re-start the read operation from that address. It is recommended that a software reset for
data be applied before the transfer is re-started after error recovery.
For any write transfer mode, the SDHC will not start data transmission until the number
of words set in the WML register are in the buffer. If the buffer is full and the Host
System does not read data in time, the SDHC will stop the SDHC_DCLK to avoid the
data buffer over-run situation.
52.5.1.3 Data buffer and block size
The user needs to know the buffer size, for the buffer operation during a data transfer, to
utilize it in the most optimized way. In the SDHC, the only data buffer can hold up to 128
words (32-bit), and the watermark levels for write and read can be configured
respectively. For both read and write, the watermark level can be from 1 word to the
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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