K60P100M100SF2RM Datasheet, PDF (1625/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

802. ^.11
MAC header
IV
Chapter 52 Secured digital host controller (SDHC)
544 Bytes WLAN Frame
Frame Body
ICV
FCS
WLAN Frame is divided equally into 64 byte blocks plus the remainder 32 bytes
Data
64 bytes
Data
64 bytes
Data
64 bytes
Data
32 bytes
SDIO Data
block #1
SDIO Data
block #2
SDIO Data
block #8
SDIO Data
32 bytes
E ight 64 byt e block s ar e sen t in B lock t r ansf er m ode and t he r em ainder
32 byt es ar e sent in B yt e T r ansf er m ode
CM D53
SDIO Data
block #1
SDIO Data
block #2
SDIO Data
block #8
CM D53
SDIO Data
32 bytes
Figure 52-30. Example for dividing large data transfers
52.5.1.5 External DMA request
When the internal DMA is not in use, and external DMA request is enabled, the data
buffer will generate a DMA request to the system. During a write operation, when the
number of WRWML words can be held in the buffer free space, a DMA request is sent ,
informing the host system of a DMA write. The IRQSTAT[BWR] bit is also set, as long
as the IRQSTATEN[BWRSEN] bit is set. The DMA request is immediately de-asserted
when an access to the DATPORT register is made. If the buffer's free space still meets
the watermark condition, the DMA request is asserted again after a cycle.
On read operation, when the number of RDWML words are already in the buffer, a DMA
request is sent , informing the host system for a DMA read. The IRQSTAT[BRR] bit is
also set, as long as the IRQSTATEN[BRRSEN] bit is set. The DMA request is
immediately de-asserted when an access to the DATPORT register is made. If the
buffer's data still meets the watermark condition, the DMA request is asserted again after
a cycle.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1625