K60P100M100SF2RM Datasheet, PDF (1263/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 45 Universal Serial Bus OTG Controller (USBOTG)
In Host mode ENDPT0 is used to determine the handshake, retry and low speed
characteristics of the host transfer. For Host mode control, bulk and interrupt transfers the
EPHSHK bit should be set to 1. For Isochronous transfers it should be set to 0. Common
values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt
transfers, and 0x4C for Isochronous transfers.
Addresses: 4007_2000h base + C0h offset + (4d × n), where n = 0d to 15d
Bit
7
6
5
4
3
Read
0
HOSTWOHUB RETRYDIS
EPCTLDIS EPRXEN
Write
Reset
0
0
0
0
0
2
EPTXEN
0
1
EPSTALL
0
0
EPHSHK
0
USBx_ENDPTn field descriptions
Field
7
HOSTWOHUB
6
RETRYDIS
5
Reserved
4
EPCTLDIS
3
EPRXEN
2
EPTXEN
1
EPSTALL
0
EPHSHK
Description
This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0). When set
this bit allows the host to communicate to a directly connected low speed device. When cleared, the host
produces the PRE_PID then switch to low speed signaling when sending a token to a low speed device
as required to communicate with a low speed device through a hub.
This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0). When set
this bit causes the host to not retry NAK'ed (Negative Acknowledgement) transactions. When a
transaction is NAKed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt is
set. When this bit is cleared NAKed transactions is retried in hardware. This bit must be set when the host
is attempting to poll an interrupt endpoint.
This read-only field is reserved and always has the value zero.
This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This
applies if and only if the EPRXEN and EPTXEN bits are also set.
This bit, when set, enables the endpoint for RX transfers.
This bit, when set, enables the endpoint for TX transfers.
When set this bit indicates that the endpoint is called. This bit has priority over all other control bits in the
EndPoint Enable Register, but it is only valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint
causes the USB Module to return a STALL handshake. After an endpoint is stalled it requires intervention
from the Host Controller.
When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This
bit is generally set unless the endpoint is Isochronous.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1263