K60P100M100SF2RM Datasheet, PDF (813/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 34 Analog-to-Digital Converter (ADC)
Table 34-44. Data result register description (continued)
Conversion
mode
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Format
11-bit differential S S S S S S D D D D D D D D D D Sign extended
2's complement
10-bit single-
ended
0 0 0 0 0 0 D D D D D D D D D D Unsigned right
justified
9-bit differential S S S S S S S S D D D D D D D D Sign extended
2's complement
8-bit single-
ended
0 0 0 0 0 0 0 0 D D D D D D D D Unsigned right
justified
NOTE
S: Sign bit or sign bit extension;
D: Data (2's complement data if indicated)
Addresses: ADC0_RA is 4003_B000h base + 10h offset = 4003_B010h
ADC0_RB is 4003_B000h base + 14h offset = 4003_B014h
ADC1_RA is 400B_B000h base + 10h offset = 400B_B010h
ADC1_RB is 400B_B000h base + 14h offset = 400B_B014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
D
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_Rn field descriptions
Field
31–16
Reserved
15–0
D
Description
This read-only field is reserved and always has the value zero.
Data result
34.3.5 Compare value registers (ADCx_CVn)
The compare value registers (CV1 and CV2) contain a compare value used to compare
with the conversion result when the compare function is enabled (ACFE=1). This register
is formatted the same for both bit position definition and value format (unsigned or sign-
extended 2's complement) as the data result registers (Rn) in the different modes of
operation. Therefore, the compare function only uses the compare value register bits that
are related to the ADC mode of operation.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
813