K60P100M100SF2RM Datasheet, PDF (968/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Definition
FTMx_FMS field descriptions (continued)
Field
7
FAULTF
Fault Detection Flag
Description
Represents the logic OR of the individual FAULTFj bits (where j = 3, 2, 1, 0). Clear FAULTF by reading
the FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no existing fault
condition at the enabled fault inputs. Writing a 1 to FAULTF has no effect.
If another fault condition is detected in an enabled fault input before the clearing sequence is completed,
the sequence is reset so FAULTF remains set after the clearing sequence is completed for the earlier
fault condition. FAULTF is also cleared when FAULTFj bits are cleared individually.
6
WPEN
0 No fault condition was detected.
1 A fault condition was detected.
Write Protection Enable
The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared
when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect.
5
FAULTIN
0 Write protection is disabled. Write protected bits can be written.
1 Write protection is enabled. Write protected bits cannot be written.
Fault Inputs
Represents the logic OR of the enabled fault inputs after their filter (if their filter is enabled) when fault
control is enabled.
4
Reserved
3
FAULTF3
0 The logic OR of the enabled fault inputs is 0.
1 The logic OR of the enabled fault inputs is 1.
This read-only field is reserved and always has the value zero.
Fault Detection Flag 3
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF3 by reading the FMS register while FAULTF3 is set and then writing a 0 to FAULTF3 while
there is no existing fault condition at the the corresponding fault input. Writing a 1 to FAULTF3 has no
effect. FAULTF3 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF3 remains set after the clearing sequence is completed for
the earlier fault condition.
2
FAULTF2
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
Fault Detection Flag 2
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF2 by reading the FMS register while FAULTF2 is set and then writing a 0 to FAULTF2 while
there is no existing fault condition at the the corresponding fault input. Writing a 1 to FAULTF2 has no
effect. FAULTF2 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF2 remains set after the clearing sequence is completed for
the earlier fault condition.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
968
Freescale Semiconductor, Inc.