K60P100M100SF2RM Datasheet, PDF (1580/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_XFERTYP field descriptions (continued)
Field
3
Reserved
2
AC12EN
0b Write (host to card)
1b Read (card to host)
Description
This read-only field is reserved and always has the value zero.
Auto CMD12 Enable
Multiple block transfers for memory require a CMD12 to stop the transaction. When this bit is set to 1, the
SDHC will issue a CMD12 automatically when the last block transfer has completed. The host driver shall
not set this bit to issue commands that do not require CMD12 to stop a multiple block data transfer. In
particular, secure commands defined in File Security Specification (see reference list) do not require
CMD12. In single block transfer, the SDHC will ignore this bit no matter if it is set or not.
1
BCEN
0b Disable
1b Enable
Block Count Enable
This bit is used to enable the Block Count register, which is only relevant for multiple block transfers.
When this bit is 0, the internal counter for block is disabled, which is useful in executing an infinite
transfer.
0
DMAEN
0b Disable
1b Enable
DMA Enable
This bit enables DMA functionality. If this bit is set to 1, a DMA operation shall begin when the host driver
sets the DPSEL bit of this register. Whether the simple DMA, or the advanced DMA, is active depends on
the PROCTL[DMAS].
0b Disable
1b Enable
52.4.5 Command Response 0 (SDHC_CMDRSP0)
This register is used to store part 0 of the response bits from the card.
Address: SDHC_CMDRSP0 is 400B_1000h base + 10h offset = 400B_1010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMDRSP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_CMDRSP0 field descriptions
Field
31–0
CMDRSP0
Command Response 0
Description
1580
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.