K60P100M100SF2RM Datasheet, PDF (558/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
selected or by writing a new trim value to the C4[FCTRIM] bits when the fast IRC clock
is selected. The internal reference clock period is proportional to the trim value written.
C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits
affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes.
C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK
frequency if the MCG is in FEI mode.
Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and
C1[IREFSTEN], otherwise this clock is disabled in Stop mode.
24.4.4 External Reference Clock
The MCG module can support an external reference clock in all modes. Refer to the
device datasheet for external reference frequency range. When C1[IREFS] is set, the
external reference clock will not be used by the FLL or PLL. In these modes, the
frequency can be equal to the maximum frequency the chip-level timing specifications
will support.
If the CME is asserted the slow internal reference clock is enabled along with the enabled
external clock monitor. For the case when C6[CME]=1, a loss of clock is detected if the
OSC external reference falls below a minimum frequency (f_{loc_high} or f_{loc_low} depending
on C2[RANGE]).
Upon detect of a loss of clock event, the MCU generates a system reset if the respective
LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG
generates a LOCS interrupt request.
24.4.5 MCG Fixed Frequency Clock
The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock
source for other on-chip peripherals. This clock is driven by either the slow clock from
the internal reference clock generator or the external reference clock from the Crystal
Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is
selected by C1[IREFS]. Additionally, this clock is divided by two.
This clock is synchronized to the peripheral bus clock and is only valid when it’s
frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is
disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI
mode. This clock is also disabled in Stop mode. The FLL reference clock must be set
within the valid frequency range for the MCGFFCLK.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
558
Freescale Semiconductor, Inc.