K60P100M100SF2RM Datasheet, PDF (1634/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
CLR_CRC
ZERO
CRC_IN
CRC
Bus [0]
CRC
Bus [1]
CRC
Bus [2]
CRC
Bus [3]
CRC
Bus [4]
CRC
Bus [5]
CRC
Bus [6]
CRC OUT
Figure 52-34. Command CRC Shift Register
The CRC polynomials for the CMD are as follows:
Generator polynomial: G(x) = x⁷ + x³ + 1
M(x) = (first bit) * xⁿ + (second bit) * x^n-1 +...+ (last bit) * x⁰
CRC[6:0] = Remainder [(M(x) * x⁷) / G(x)]
52.5.3.4 Data agent
The data agent deals with the transactions on the eight data lines. Moreover, this module
also detects the busy state on the DAT[0] line, and generate the read wait state by the
request from the transceiver. The CRC polynomials for the DAT are as follows:
Generator polynomial: G(x) = x¹⁶ + x¹² + x⁵
+1
M(x) = (first bit) * xⁿ + (second bit) * x^n-1 +...+ (last bit) * x⁰
CRC[15:0] = Remainder [(M(x) * x¹⁶) / G(x)]
52.5.4 Clock & reset manager
This module controls all the reset signals within the SDHC.
There are four kinds of reset signals within SDHC:
1. Hardware reset.
2. Software reset for all.
3. Software reset for the data part.
4. Software reset for the command part.
All these signals are fed into this module and stable signals are generated inside the
module to reset all other modules. The module also gates off all the inside signals.
There are three clocks inside the SDHC:
1634
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.