K60P100M100SF2RM Datasheet, PDF (1152/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
44.3.11 Physical Address Lower Register (ENET_PALR)
PALR contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address
recognition process to compare with the DA (destination address) field of receive frames
with an individual DA. In addition, this register is used in bytes 0 through 3 of the six-
byte source address field when transmitting PAUSE frames. This register is not reset and
you must initialize it.
Address: ENET_PALR is 400C_0000h base + E4h offset = 400C_00E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PADDR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_PALR field descriptions
Field
31–0
PADDR1
Pause address
Description
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used
for exact match and the source address field in PAUSE frames.
44.3.12 Physical Address Upper Register (ENET_PAUR)
PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address
recognition process to compare with the DA (destination address) field of receive frames
with an individual DA. In addition, this register is used in bytes 4 and 5 of the six-byte
source address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a
constant type field (0x8808) for transmission of PAUSE frames. The upper 16 bits of this
register are not reset and you must initialize it.
Address: ENET_PAUR is 400C_0000h base + E8h offset = 400C_00E8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PADDR2
W
TYPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
ENET_PAUR field descriptions
Field
31–16
PADDR2
Description
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the
source address field in PAUSE frames.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.