K60P100M100SF2RM Datasheet, PDF (1596/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
The table below shows the relationship between the CTOE and the CC bits.
Table 52-19. SDHC status for CTOE/CC bit combinations
Command complete
0
X
1
Command timeout error
0
1
0
Meaning of the status
X
Response not received within 64
SDCLK cycles
Response received
The table below shows the relationship between the Transfer Complete and the Data
Timeout Error.
Table 52-20. SDHC status for data timeout error/transfer complete bit combinations
Transfer complete
0
0
1
Data timeout error
0
1
X
Meaning of the status
X
Timeout occurred during transfer
Data transfer complete
The table below shows the relationship between the command CRC error (CCE) and
command timeout error (CTOE).
Table 52-21. SDHC status for CCE/CTOE Bit Combinations
Command complete
0
0
1
1
Command timeout error
0
1
0
1
Meaning of the status
No error
Response timeout error
Response CRC error
CMD line conflict
1596
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.