K60P100M100SF2RM Datasheet, PDF (721/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
FB_CLK
FB_A[Y]
Address
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
FB_CSn
AA=1
AA=0
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
AA=1
AA=0
TSIZ=00
Figure 29-35. Longword-Write Transfer
29.4.6.4 Timing Variations
The FlexBus module has several features that can change the timing characteristics of a
basic read- or write-bus cycle to provide additional address setup, address hold, and time
for a device to provide or latch data.
29.4.6.4.1 Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn
registers. Wait states can give the peripheral or memory more time to return read data or
sample write data.
The following figures show the basic read and write bus cycles (also shown in Figure
29-27 and Figure 29-32) with the default of no wait states respectively.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
721