K60P100M100SF2RM Datasheet, PDF (396/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Application Information
• Creating a new memory region—Load the appropriate region descriptor into an
available RGDn, using four sequential 32-bit writes. The hardware assists in the
maintenance of the valid bit, so if this approach is followed, there are no coherency
issues with the multi-cycle descriptor writes. (Clearing RGDn_Word3[VLD] deletes/
removes an existing memory region.)
• Altering only access privileges—To not affect the valid bit, write to the alternate
version of the access control word (RGDAACn), so there are no coherency issues
involved with the update. When the write completes, the memory region's access
rights switch instantaneously to the new value.
• Changing a region's start and end addresses—Write a minimum of three words to the
region descriptor (RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end
addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most
situations, all four words of the region descriptor are rewritten.
• Accessing the MPU—Allocate a region descriptor to restrict MPU access to
supervisor mode from a specific master.
• Detecting an access error—The current bus cycle is terminated with an error
response and EARn and EDRn capture information on the faulting reference. The
error-terminated bus cycle typically initiates an error response in the originating bus
master. For example, a processor core may respond with a bus error exception, while
a data movement bus master may respond with an error interrupt. The processor can
retrieve the captured error address and detail information simply by reading
E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data.
• Overlapping region descriptors—Applying overlapping regions often reduces the
number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are
logically summed together (the boolean OR operator).
The following dual-core system example contains four bus masters: the two
processors (CP0, CP1) and two DMA engines (DMA1, a traditional data movement
engine transferring data between RAM and peripherals and DMA2, a second engine
transferring data to/from the RAM only). Consider the following region descriptor
assignments:
Table 18-81. Overlapping Region Descriptor Example
Region Description
CP0 code
CP1 code
RGDn
CP0
0
rwx
1
r--
CP1
DMA1
DMA2
r--
—
—
rwx
—
—
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
396
Freescale Semiconductor, Inc.