K60P100M100SF2RM Datasheet, PDF (1606/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_IRQSIGEN field descriptions (continued)
Field
2
BGEIEN
1
TCIEN
0
CCIEN
0b Masked
1b Enabled
Block Gap Event Interrupt Enable
0b Masked
1b Enabled
Transfer Complete Interrupt Enable
0b Masked
1b Enabled
Command Complete Interrupt Enable
0b Masked
1b Enabled
Description
52.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)
When the AC12ESEN bit in the Status register is set, the host driver shall check this
register to identify what kind of error the Auto CMD12 indicated. This register is valid
only when the Auto CMD12 Error status bit is set.
The following table shows the relationship between the Auto CMGD12 CRC error and
the Auto CMD12 command timeout error.
Table 52-25. Relationship Between Command CRC Error and Command Timeout Error for
Auto CMD12
Auto CMD12 CRC error
0
0
1
1
Auto CMD12 timeout error
0
1
0
1
Type of error
No error
Response timeout error
Response CRC error
CMD line conflict
Changes in Auto CMD12 Error Status register can be classified in three scenarios:
1. When the SDHC is going to issue an auto CMD12.
• Set bit 0 to 1 if the auto CMD12 can't be issued due to an error in the previous
command.
• Set bit 0 to 0 if the auto CMD12 is issued.
2. At the end bit of an auto CMD12 response.
1606
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.