K60P100M100SF2RM Datasheet, PDF (1020/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
update INVCTRL register at
each rising edge of system clock
no =
rising edge
of system
clock ?
= yes
update INVCTRL
with its buffer value
end
begin
0 = _INVC = 1
bit ?
INVCTRL is updated
by software trigger
1 = _SWINVC = 0
bit ?
0=
SWSYNC
software
trigger
bit ?
=1
end
update INVCTRL
with its buffer value
end
update INVCTRL register by
PWM synchronization
1 = _SYNCMODE = 0
bit ?
end
enhanced PWM synchronization
INVCTRL is updated
by hardware trigger
0 = _HWINVC = 1
bit ?
end
hardware
trigger
TRIGn
bit ?
=0
=1
wait hardware trigger n
update INVCTRL
with its buffer value
HWTRIGMODE ^{= 1}
bit ?
=0
clear TRIGn bit
end
Figure 39-218. INVCTRL Register Synchronization Flowchart
39.4.11.9 SWOCTRL Register Synchronization
The SWOCTRL register synchronization updates the SWOCTRL register with its buffer
value.
1020
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.