K60P100M100SF2RM Datasheet, PDF (1007/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

channel (n+1) match
FTM counter
channel (n) match
Chapter 39 FlexTimer (FTM)
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n+1) output
with COMP = 0
channel (n+1) output
with COMP = 1
Figure 39-203. Channel (n+1) Output in Complementary Mode with (ELSnB:ELSnA = 1:0)
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
with ELSnB:ELSnA = X:1
channel (n+1) output
with COMP = 0
channel (n+1) output
with COMP = 1
Figure 39-204. Channel (n+1) Output in Complementary Mode with (ELSnB:ELSnA = X:1)
39.4.10 Registers Updated from Write Buffers
39.4.10.1 CNTIN Register Update
If (CLKS[1:0] = 0:0) then CNTIN register is updated when CNTIN register is written
(independent of FTMEN bit).
If (FTMEN = 0) or (CNTINC = 0) then CNTIN register is updated at the next system
clock after CNTIN was written.
If (FTMEN = 1), (SYNCMODE = 1) and (CNTINC = 1) then CNTIN register is updated
by the CNTIN register synchronization (CNTIN Register Synchronization).
39.4.10.2 MOD Register Update
If (CLKS[1:0] = 0:0) then MOD register is updated when MOD register is written
(independent of FTMEN bit).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1007