K60P100M100SF2RM Datasheet, PDF (808/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register Definition
ADCx_SC1n field descriptions (continued)
Field
6
AIEN
Interrupt enable
Description
AIEN enables conversion complete interrupts. When COCO becomes set while the respective AIEN is
high, an interrupt is asserted.
5
DIFF
0 Conversion complete interrupt disabled.
1 Conversion complete interrupt enabled.
Differential mode enable
DIFF configures the ADC to operate in differential mode. When enabled, this mode automatically selects
from the differential channels, and changes the conversion algorithm and the number of cycles to
complete a conversion.
4–0
ADCH
0 Single-ended conversions and input channels are selected.
1 Differential conversions and input channels are selected.
Input channel select
The ADCH bits form a 5-bit field that selects one of the input channels. The input channel decode
depends on the value of the DIFF bit. DAD0-DAD3 are associated with the input pin pairs DADPx and
DADMx.
The successive approximation converter subsystem is turned off when the channel select bits are all set
(ADCH = 11111). This feature allows for explicit disabling of the ADC and isolation of the input channel
from all sources. Terminating continuous conversions this way prevents an additional single conversion
from being performed. It is not necessary to set the channel select bits to all ones to place the ADC in a
low-power state when continuous conversions are not enabled because the module automatically enters
a low-power state when a conversion completes.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
808
Freescale Semiconductor, Inc.