K60P100M100SF2RM Datasheet, PDF (1602/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_IRQSTATEN field descriptions (continued)
Field
24
AC12ESEN
23
Reserved
22
DEBESEN
21
DCESEN
20
DTOESEN
19
CIESEN
18
CEBESEN
17
CCESEN
16
CTOESEN
15–9
Reserved
8
CINTSEN
Auto CMD12 Error Status Enable
Description
0b Masked
1b Enabled
This read-only field is reserved and always has the value zero.
Data End Bit Error Status Enable
0b Masked
1b Enabled
Data CRC Error Status Enable
0b Masked
1b Enabled
Data Timeout Error Status Enable
0b Masked
1b Enabled
Command Index Error Status Enable
0b Masked
1b Enabled
Command End Bit Error Status Enable
0b Masked
1b Enabled
Command CRC Error Status Enable
0b Masked
1b Enabled
Command Timeout Error Status Enable
0b Masked
1b Enabled
This read-only field is reserved and always has the value zero.
Card Interrupt Status Enable
If this bit is set to 0, the SDHC will clear the interrupt request to the system. The card interrupt detection is
stopped when this bit is cleared and restarted when this bit is set to 1. The host driver should clear the
this bit before servicing the card interrupt and should set this bit again after all interrupt requests from the
card are cleared to prevent inadvertent interrupts.
7
CRMSEN
0b Masked
1b Enabled
Card Removal Status Enable
Table continues on the next page...
1602
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.