K60P100M100SF2RM Datasheet, PDF (1433/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

49.4.6 Slave Mode Operation Constraints
Chapter 49 SPI (DSPI)
Slave mode logic shift register is buffered. This allows data streaming operation, when
the DSPI is permanently selected and data is shifted in with a constant rate.
The transmit data is transferred at second SCK clock edge of the each frame to the shift
register if the SS signal is asserted and any time when transmit data is ready and SS
signal is negated.
Received data is transferred to the receive buffer at last SCK edge of each frame, defined
by frame size programmed to the CTAR0/1 register. Then the data from the buffer is
transferred to the RXFIFO or DDR register.
If the SS negates before that last SCK edge, the data from shift register is lost.
This buffering scheme allows to operate slave clock with higher frequency than the
system frequency. The clocks relationship is defined by the following equation.
FrameSize is the value of the CTAR0/1[FMSZ] field plus one.
3
49.4.7 Interrupts/DMA Requests
The DSPI has several conditions that can only generate interrupt requests and two
conditions that can generate interrupt or DMA requests. The following table lists these
conditions.
Table 49-112. Interrupt and DMA Request Conditions
Condition
End of Queue (EOQ)
TX FIFO Fill
Transfer Complete
TX FIFO Underflow
RX FIFO Drain
RX FIFO Overflow
Flag
EOQF
TFFF
TCF
TFUF
RFDF
RFOF
Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
DMA
Yes
Yes
Each condition has a flag bit in the DSPI Status Register (SR) and an Request Enable bit
in the DSPI DMA/Interrupt Request Select and Enable Register (RSER). The TX FIFO
Fill Flag (TFFF) and RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA
requests depending on the TFFF_DIRS and RFDF_DIRS bits in the RSER.
The DSPI module also provides a global interrupt request line, which is asserted when
any of individual interrupt requests lines is asserted.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1433