K60P100M100SF2RM Datasheet, PDF (1111/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 43 Real Time Clock (RTC)
Write accesses to any register by non-supervisor mode software, when the supervisor
access bit in the control register is clear, will terminate with a bus error.
Read accesses by non-supervisor mode software complete as normal.
Writing to a register protected by the write access register or lock register does not
generate a bus error, but the write will not complete.
Reading a register protected by the read access register does not generate a bus error, but
the register will read zero.
Absolute
address
(hex)
RTC memory map
Register name
Width
(in bits)
Access
Reset value
4003_D000 RTC Time Seconds Register (RTC_TSR)
32
R/W 0000_0000h
4003_D004 RTC Time Prescaler Register (RTC_TPR)
32
R/W 0000_0000h
4003_D008 RTC Time Alarm Register (RTC_TAR)
32
R/W 0000_0000h
4003_D00C RTC Time Compensation Register (RTC_TCR)
32
R/W 0000_0000h
4003_D010 RTC Control Register (RTC_CR)
32
R/W 0000_0000h
4003_D014 RTC Status Register (RTC_SR)
32
R/W 0000_0001h
4003_D018 RTC Lock Register (RTC_LR)
32
R/W 0000_00FFh
4003_D01C RTC Interrupt Enable Register (RTC_IER)
32
R/W 0000_0007h
4003_D800 RTC Write Access Register (RTC_WAR)
32
R/W 0000_00FFh
4003_D804 RTC Read Access Register (RTC_RAR)
32
R/W 0000_00FFh
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43.2.1 RTC Time Seconds Register (RTC_TSR)
Address: RTC_TSR is 4003_D000h base + 0h offset = 4003_D000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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