K60P100M100SF2RM Datasheet, PDF (17/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................457
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................458
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................459
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................460
21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................461
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................462
21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................463
21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................463
21.3.14 Error Register (DMA_ERR)........................................................................................................................466
21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................468
21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................470
21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................471
21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................472
21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................472
21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................473
21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................474
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................475
21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................476
21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................476
21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................477
21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................477
21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................478
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........479
21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................480
21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................482
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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