K60P100M100SF2RM Datasheet, PDF (393/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
4–3
M0SM
2–0
M0UM
Chapter 18 Memory Protection Unit (MPU)
MPU_RGDAACn field descriptions (continued)
Description
Bus master 0 supervisor mode access control
See M3SM description.
Bus master 0 user mode access control
See M3UM description.
18.4 Functional Description
In this section, the functional operation of the MPU is detailed, including the operation of
the access evaluation macro and the handling of error-terminated bus cycles.
18.4.1 Access Evaluation Macro
The basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in the following
figure, the access evaluation macro inputs the crossbar bus address phase signals and the
contents of a region descriptor (RGDn) and performs two major functions: region hit
determination and detection of an access protection violation. The following figure shows
a functional block diagram.
Address
start
≥
end
≤
RGDn
r,w,x
hit_b
error
≥
≥
MPU_EDRn
(hit AND error)
Access not allowed
(no hit OR error)
Figure 18-80. MPU Access Evaluation Macro
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
393