K60P100M100SF2RM Datasheet, PDF (1635/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

1. Bus clock.
2. SDHC clock.
3. System clock.
Chapter 52 Secured digital host controller (SDHC)
The module monitors the activities of all other modules, supplies the clocks for them, and
when enabled, automatically gates off the corresponding clocks.
52.5.5 Clock generator
The clock generator generates the SDHC_CLK by peripheral source clock in two stages.
The following diagram illustrates the structure of the divider. The term "base" represents
the frequency of peripheral source clock.
1st divisor
Base
by 1, 2, 3, ..., 16
2nd divisor
SD_CLK
DIV
by (1*), 2, 4, ..., 256
(SD_CLK_2X*)
Figure 52-35. Two stages of the clock divider
The first stage outputs an intermediate clock (DIV), which can be base, base/2, base/3, ...,
or base/16.
The second stage is a prescaler, and outputs the actual clock (SDHC_CLK). This clock is
the driving clock for all sub modules of the SD protocol unit, and the sync FIFOs to
synchronize with the data rate from the internal data buffer. The frequency of the clock
output from this stage, can be DIV, DIV/2, DIV/4,..., or DIV/256. Thus the highest
frequency of the SDHC_CLK is base, and the next highest is base/2, while the lowest
frequency is base/4096. If the base clock is of equal duty ratio (usually true), the duty
cycle of SDHC_CLK is also 50%, even when the compound divisor is an odd value.
52.5.6 SDIO card interrupt
This section discusses SDIO interrupt handling.
52.5.6.1 Interrupts in 1-bit mode
In this case the DAT[1] pin is dedicated to providing the interrupt function. An interrupt
is asserted by pulling the DAT[1] low from the SDIO card, until the interrupt service is
finished to clear the interrupt.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1635