K60P100M100SF2RM Datasheet, PDF (322/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Mode Control Memory Map/Register Definition
MC_SRSL field descriptions (continued)
Field
6
PIN
0 Reset not caused by POR
1 Reset caused by POR
External reset pin
Description
Indicates reset was caused by an active-low level on the external RESETpin.
5
COP
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
Computer Operating Properly (COP) Watchdog
Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by disabling
the watchdog. For more information, see the watchdog chapter.
4–3
Reserved
2
LOC
0 Reset not caused by COP timeout
1 Reset caused by COP timeout
This read-only field is reserved and always has the value zero.
Loss-of-clock reset
Indicates reset was caused by a loss of external clock. The MCG clock monitor must be enabled for a loss
of clock to be detected. See the MCG chapter for information on enabling the clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
Low-voltage detect reset
LVD
If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is
also set by POR.
0
WAKEUP
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
Low-leakage wakeup reset
Reset was caused by an enabled LLWU module wakeup source while the device was in LLS or VLLS
modes. Wakeup sources in LLS is limited to the RESET pin. In VLLS, any enabled wakeup source causes
a reset. This bit is cleared by any reset except WAKEUP.
0 Reset not caused by LLWU module wakeup source
1 Reset caused by LLWU module wakeup source
13.2.3 Power Mode Protection Register (MC_PMPROT)
This write-once register allows low power or low leakage modes to be entered. The
actual enabling of the low power or low leakage modes is done by configuring the power
mode control register (PMCTRL).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
322
Freescale Semiconductor, Inc.