K60P100M100SF2RM Datasheet, PDF (198/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Reset
6.2.3 Debug resets
The following sections detail the debug resets available on the device.
6.2.3.1 JTAG reset
The JTAG module generate a system reset when certain IR codes are selected. This
functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are
active. The reset source from the JTAG module is released when any other IR code is
selected. A JTAG reset causes the SRSH[JTAG] bit to set.
6.2.3.2 nTRST reset
The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin
allows the debugger to gain control of the TAP controller state machine (after exiting
LLS or VLLSx) without resetting the state of the debug modules.
The nTRST pin does not cause a system reset.
6.2.3.3 Resetting the Debug subsystem
Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug
modules. However, as explained below, using the CDBGRSTREQ bit does not reset all
debug-related registers.
CDBGRSTREQ resets the debug-related registers within the following modules:
• SWJ-DP
• AHB-AP
• ETM
• ATB replicators
• ATB upsizers
• ATB funnels
• ETB
• TPIU
• MDM-AP (MDM control and status registers)
• MCM (ETB “Almost Full” logic)
CDBGRSTREQ does not reset the debug-related registers within the following modules:
• CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• FPB
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
198
Freescale Semiconductor, Inc.