K60P100M100SF2RM Datasheet, PDF (307/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Mode
VLPR
VLPW
VLPS
LLS
VLLS3
VLLS2
VLLS1
Table 13-1. Power modes (continued)
Chapter 13 Mode Controller
Description
The Core Clock, System Clock and Bus Clocks maximum frequency is restricted to 2MHz max,
Flash Clock is restricted to 1MHz. The slow IRC within the MCG must not be enabled when VLPR
is entered.
In ARM architectures, the Core Clock to the ARM Cortex-M4 core is shut off. The System Clock
continues to operate; Bus Clocks if enabled continue to operate; System and Bus clock restricted to
2MHz max, Flash Clock is restricted to 1MHz
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock and Bus Clocks are stopped after all stop acknowledge signals from
supporting peripherals are valid. MCU is placed in a low leakage mode by reducing the voltage to
internal logic. Internal logic states are retained.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering
down the internal logic. System RAM contents retained and I/O states held. Internal logic states are
not retained.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering
down the internal logic and part of system RAM. The rest of the system RAM contents are retained
and I/O states held. FlexRAM contents can optionally be retained. Internal logic states are not
retained.
NOTE: See the device's Chip Configuration details for the amount of SRAM retained in VLLS2
mode.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering
down the internal logic and all system RAM. A 32-byte register file (available in all modes) contents
retained and I/O states held. Internal logic states are not retained.
13.1.2.1 Power Mode Transitions
The following shows the power mode state transitions available on the device.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
307