K60P100M100SF2RM Datasheet, PDF (1691/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
31–25
Reserved
24
RFRC
23
TRFC
22–19
Reserved
18
CMDAU
17
CMDDU
16
RXT
15
RDR1
Chapter 53 Integrated interchip sound (I2S)
I2Sx_ISR field descriptions
Description
This read-only field is reserved and always has the value zero.
Receive Frame Complete.
This flag is set at the end of the frame during which receiver is disabled. If receive frame and clock are not
disabled in the same frame, this flag is also set at the end of the frame in which receive frame and clock
are disabled. See description of CR[RFRCLKDIS] bit for more details on how to disable receiver frame
and clock or keep them enabled after receiver is disabled.
0 End of frame not reached.
1 End of frame reached after disabling CR[RE] or disabling CR[RFRCLKDIS], when receiver is already
disabled.
Transmit Frame Complete.
This flag is set at the end of the frame during which transmitter is disabled. If transmit frame and clock are
not disabled in the same frame, this flag is also set at the end of the frame in which transmit frame and
clock are disabled. See description of CR[TFRCLKDIS] bit for more details on how to disable transmit
frame and clock or keep them enabled after transmitter is disabled.
0 End of frame not reached.
1 End of frame reached after disabling CR[TE] or disabling CR[TFRCLKDIS], when transmitter is
already disabled.
This read-only field is reserved and always has the value zero.
Command Address Register Updated.
This bit causes the command address Updated interrupt (when IER[CMDAUEN] bit is set). This status bit
is set each time there is a difference in the previous and current value of the received command address.
This bit is cleared on reading the ACADD register.
0 No change in ACADD register.
1 ACADD register updated with different value.
Command Data Register Updated.
This bit causes the command data updated interrupt (when IER[CMDDUEN] bit is set). This status bit is
set each time there is a difference in the previous and current value of the received command data. This
bit is cleared on reading the ACDAT register.
0 No change in ACDAT register.
1 ACDAT register updated with different value.
Receive Tag Updated.
This status bit is set each time there is a difference in the previous and current value of the received tag. It
causes the receive tag interrupt (if IER[RXTEN] bit is set). This bit is cleared on reading the ATAG
register.
0 No change in ATAG register.
1 ATAG register updated with different value.
Receive Data Ready 1.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1691