K60P100M100SF2RM Datasheet, PDF (179/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 5
Clock Distribution
5.1 Introduction
The MCG module controls which clock source is used to derive the system clocks. The
clock generation logic divides the selected clock source into a variety of clock domains,
including the clocks for the system bus masters, system bus slaves, and flash memory.
The clock generation logic also implements module-specific clock gating to allow
granular shutoff of modules.
The primary clocks for the system are generated from the MCGOUTCLK clock. The
clock generation circuitry provides several clock dividers that allow different portions of
the device to be clocked at different frequencies. This allows for trade-offs between
performance and power dissipation.
Various modules, such as the USB OTG Controller, have module-specific clocks that can
be generated from the MCGPLLCLK or MCGFLLCLK clock. In addition, there are
various other module-specific clocks that have other alternate sources. Clock selection for
most modules is controlled by the SOPT registers in the SIM module.
5.2 Programming model
The selection and multiplexing of system clock sources is controlled and programmed via
the MCG module. The setting of clock dividers and module clock gating for the system
are programmed via the SIM module. Reference those sections for detailed register and
bit descriptions.
5.3 High-Level device clocking diagram
The following system oscillator, MCG, and SIM module registers control the
multiplexers, dividers, and clock gates shown in the below figure:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
179