K60P100M100SF2RM Datasheet, PDF (187/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Module
SDHC
I²S
GPIO
TSI
Table 5-2. Module clocks (continued)
Bus interface clock
System clock
Bus clock
Internal clocks
SDHC clock
I²S master clock
Human-machine interfaces
System clock
—
Bus clock
LPO, ERCLK32K,
MCGIRCLK
Chapter 5 Clock Distribution
I/O interface clocks
SDHC_DCLK
I2S_TX_BCLK,
I2S_RX_BCLK
—
—
5.7.1 PMC 1-kHz LPO clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all
modes of operation, including all low power modes. This 1-kHz source is commonly
referred to as LPO clock or 1-kHz LPO clock.
5.7.2 WDOG clocking
The WDOG may be clocked from two clock sources as shown in the following figure.
LPO
Bus clock
WDOG clock
WDOG_STCTRLH[CLKSRC]
Figure 5-2. WDOG clock generation
5.7.3 Debug trace clock
The debug trace clock source can be clocked as shown in the following figure.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
187