K60P100M100SF2RM Datasheet, PDF (1230/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
44.4.18.2 MII Interface — Transmit
On transmit, all data transfers are synchronous to MII_TXCLK rising edge. The MII data
enable signal MII_TXEN is asserted to indicate the start of a new frame and remains
asserted until the last byte of the frame is present on the MII_TXD[3:0] bus.
Between frames, MII_TXEN remains deasserted.
Preamble
SFD
CRC-32
MII_TXCLK
MII_TXD[3:0]
MII_TXEN
MII_TXER
5
04 05 06 07
08 09 0A
0F 10 11 12
13 14 15 16 17 18 19
1A
1C
1E 1F 20 21 22 23 24
25 26
27 28 29
2B
2E 2F 30
31 32
33 34
35 36 37 38 39 3B
3F 40 99
80
28
Figure 44-72. MII Transmit Operation
If a frame is received on the FIFO interface with an error (e.g., RxBD[ME] set) the frame
is subsequently transmitted with the MII_TXER error signal for one clock cycle at any
time during the packet transfer.
Preamble
SFD
CRC-32
MII_TXCLK
MII_TXD[3:0]
5
MII_TXEN
MII_TXER
Figure 44-73. MII Transmit Operation — Errored Frame
1230
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.