K60P100M100SF2RM Datasheet, PDF (1056/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
After enabling the loading points, the LDOK bit needs to be set for the load to occur. In
this case the load occurs at the next enabled loading point according to the following
conditions:
• If a new value was written to the MOD register, then the MOD register is updated
with its write buffer value.
• If a new value was written to the CNTIN register and CNTINC = 1, then the CNTIN
register is updated with its write buffer value.
• If a new value was written to the C(n)V register and SYNCENm = 1 – where m
indicates the pair channels (n) and (n+1), then the C(n)V register is updated with its
write buffer value.
• If a new value was written to the C(n+1)V register and SYNCENm = 1 – where m
indicates the pair channels (n) and (n+1), then the C(n+1)V register is updates with
its write buffer value.
FTM counter = MOD
FTM counter = C7V
FTM counter = C6V
FTM counter = C5V
FTM counter = C4V
FTM counter = C3V
FTM counter = C2V
FTM counter = C1V
FTM counter = C0V
(a)
(b)
(c)
(d)
(e)
(f)
NOTE
(a) LDOK = 0, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0
(b) LDOK = 1, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0
(c) LDOK = 0, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 1, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0
(d) LDOK = 1, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 1, CH7SEL = 0
(e) LDOK = 1, CH0SEL = 1, CH1SEL = 0, CH2SEL = 1, CH3SEL = 0, CH4SEL = 1, CH5SEL = 0, CH6SEL = 1, CH7SEL = 0
(f) LDOK = 1, CH0SEL = 1, CH1SEL = 1, CH2SEL = 1, CH3SEL = 1, CH4SEL = 1, CH5SEL = 1, CH6SEL = 1, CH7SEL = 1
Figure 39-257. Loading Points for Intermediate Load
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.