K60P100M100SF2RM Datasheet, PDF (1170/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
ENET_TGSR field descriptions (continued)
Field
0
TF0
0 Timer Flag for Channel 1 is clear
1 Timer Flag for Channel 1 is set
Copy of Timer Flag for channel 0
0 Timer Flag for Channel 0 is clear
1 Timer Flag for Channel 0 is set
Description
44.3.41 Timer Control Status Register (ENET_TCSRn)
Addresses: ENET_TCSR0 is 400C_0000h base + 608h offset = 400C_0608h
ENET_TCSR1 is 400C_0000h base + 610h offset = 400C_0610h
ENET_TCSR2 is 400C_0000h base + 618h offset = 400C_0618h
ENET_TCSR3 is 400C_0000h base + 620h offset = 400C_0620h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
TF
0
TIE
w1c
TMODE
Reset 0
Field
31–8
Reserved
7
TF
6
TIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENET_TCSRn field descriptions
Description
This read-only field is reserved and always has the value zero.
Timer Flag
Sets when input capture or output compare occurs. This flag is double buffered between the module clock
and 1588 clock domains. Clear the flag by writing a logic one to this bit when it is set.
0 Input Capture or Output Compare has not occurred
1 Input Capture or Output Compare has occurred
Timer interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
Table continues on the next page...
1170
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.