K60P100M100SF2RM Datasheet, PDF (189/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 5 Clock Distribution
NOTE
The chosen clock must remain enabled if the LPTMRx is to
continue operating in all required low-power modes.
MCGIRCLK
LPO
ERCLK32K
OSCERCLK
LPTMRx prescaler/glitch
filter clock
LPTMRx_PSR[PCS]
Figure 5-5. LPTMRx prescaler/glitch filter clock generation
5.7.6 Ethernet Clocking
• The RMII clock source is fixed to OSCERCLK and must be 50 MHz
• The MII clocks are supplied from pins and must be 25 MHz
• The IEEE 1588 timestamp clock can run up to 100 MHz, if generated from internal
clock sources. Its period must be an integer number of nanoseconds (eg: 10ns = 100
MHz, 15ns = 66.67 MHz, 20ns = 50 MHz). Its clock source is chosen as shown in
the following figure.
Core / System
clock
MCGPLLCLK or
MCGFLLCLK
OSCERCLK
Ethernet IEEE 1588
timestamp clock
ENET_1588_CLKIN
SIM_SOPT2[TIMESRC]
Figure 5-6. Ethernet IEEE1588 timestamp clock generation
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
189